Functions | |
| module | vmm_hw_in_if (rx_rdy, tx_rdy, msg, uclk, urst) |
| module | vmm_hw_out_if (tx_rdy, rx_rdy, msg, uclk, urst) |
| module | vmm_hw_clock_control (uclk, urst, rdy_for_cclk, cclk_en, rdy_for_cclk_neg, cclk_neg_en) |
| module | vmm_hw () |
| module | vmm_hw_clock (cclk, crst, crstn) |
| module | vmm_alias (w, w) |
| module vmm_alias | ( | w | , | |
| w | ||||
| ) |
Definition at line 23 of file vmm_alias.sv.
| module vmm_hw | ( | ) |
Definition at line 302 of file vmm_hw_rtl.sv.
| module vmm_hw_clock | ( | cclk | , | |
| crst | , | |||
| crstn | ||||
| ) |
Definition at line 389 of file vmm_hw_rtl.sv.
| module vmm_hw_clock_control | ( | uclk | , | |
| urst | , | |||
| rdy_for_cclk | , | |||
| cclk_en | , | |||
| rdy_for_cclk_neg | , | |||
| cclk_neg_en | ||||
| ) |
Definition at line 247 of file vmm_hw_rtl.sv.
| module vmm_hw_in_if | ( | rx_rdy | , | |
| tx_rdy | , | |||
| msg | , | |||
| uclk | , | |||
| urst | ||||
| ) |
Definition at line 109 of file vmm_hw_rtl.sv.
| module vmm_hw_out_if | ( | tx_rdy | , | |
| rx_rdy | , | |||
| msg | , | |||
| uclk | , | |||
| urst | ||||
| ) |
Definition at line 184 of file vmm_hw_rtl.sv.
![]() Intelligent Design Verification Project: VMM, Revision: 1.1.1 |
Copyright (c) 2008-2010 Intelligent Design Verification. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included here: http://www.intelligentdv.com/licenses/fdl.txt |
![]() Doxygen Version: 1.6.3 IDV SV Filter Version: 2.6.3 Sat Jun 19 12:06:55 2010 |