#include "vmm.sv"

Go to the source code of this file.
Defines | |
| #define | VMM_HW_RTL__SV |
| #define | VMM_HW_ARCH |
| #define | VMM_HW_INCL_DUT |
Functions | |
| interface | vmm_hw_in_if_itf (input logic rx_rdy, output logic tx_rdy, output logic< VMM_HW_DATA_WIDTH-1:0 > msg, input logic uclk, input logic urst, input int width, input bit< 1024 *8-1:0 > path) |
| module | vmm_hw_in_if (rx_rdy, tx_rdy, msg, uclk, urst) |
| interface | vmm_hw_out_if_itf (input logic tx_rdy, output logic rx_rdy, input logic< VMM_HW_DATA_WIDTH-1:0 > msg, input logic uclk, input logic urst, input int width, input bit< 1024 *8-1:0 > path) |
| module | vmm_hw_out_if (tx_rdy, rx_rdy, msg, uclk, urst) |
| interface | vmm_hw_clock_control_itf (input logic uclk, input logic urst, input logic rdy_for_cclk, output logic cclk_en, input logic rdy_for_cclk_neg, output logic cclk_neg_en, input bit< 1024 *8-1:0 > path, input int clock_num) |
| module | vmm_hw_clock_control (uclk, urst, rdy_for_cclk, cclk_en, rdy_for_cclk_neg, cclk_neg_en) |
| module | vmm_hw () |
| interface | vmm_hw_clock_itf (input int clock_num, input logic ck_en, input logic ckn_en, output int no_pos, output int no_neg) |
| module | vmm_hw_clock (cclk, crst, crstn) |
| #define VMM_HW_ARCH |
Definition at line 52 of file vmm_hw_rtl.sv.
| #define VMM_HW_INCL_DUT |
Definition at line 69 of file vmm_hw_rtl.sv.
| #define VMM_HW_RTL__SV |
Definition at line 29 of file vmm_hw_rtl.sv.
![]() Intelligent Design Verification Project: VMM, Revision: 1.1.0 |
Copyright (c) 2008-2010 Intelligent Design Verification. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included here: http://www.intelligentdv.com/licenses/fdl.txt |
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