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Defines | |
| #define | VMM_HW_RTL_COMPONENT_START interface |
| #define | VMM_HW_RTL_COMPONENT_END endinterface |
Functions | |
| interface | vmm_hw_in_if (rx_rdy, tx_rdy, msg, uclk, urst) |
| interface | vmm_hw_out_if (tx_rdy, rx_rdy, msg, uclk, urst) |
| interface | vmm_hw_clock_control (uclk, urst, rdy_for_cclk, cclk_en, rdy_for_cclk_neg, cclk_neg_en) |
| interface | vmm_hw_clock (cclk, crst, crstn) |
| #define VMM_HW_RTL_COMPONENT_END endinterface |
Definition at line 83 of file vmm_hw_rtl.sv.
| #define VMM_HW_RTL_COMPONENT_START interface |
Definition at line 82 of file vmm_hw_rtl.sv.
| interface vmm_hw_clock | ( | cclk | , | |
| crst | , | |||
| crstn | ||||
| ) |
Definition at line 281 of file vmm_hw_rtl.sv.
| interface vmm_hw_clock_control | ( | uclk | , | |
| urst | , | |||
| rdy_for_cclk | , | |||
| cclk_en | , | |||
| rdy_for_cclk_neg | , | |||
| cclk_neg_en | ||||
| ) |
Definition at line 186 of file vmm_hw_rtl.sv.
| interface vmm_hw_in_if | ( | rx_rdy | , | |
| tx_rdy | , | |||
| msg | , | |||
| uclk | , | |||
| urst | ||||
| ) |
Definition at line 91 of file vmm_hw_rtl.sv.
| interface vmm_hw_out_if | ( | tx_rdy | , | |
| rx_rdy | , | |||
| msg | , | |||
| uclk | , | |||
| urst | ||||
| ) |
Definition at line 138 of file vmm_hw_rtl.sv.
 Intelligent Design Verification Project: VMM, Revision: 1.0.1 |
Copyright (c) 2008 Intelligent Design Verification. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included here: http://www.intelligentdv.com/licenses/fdl.txt |
 Doxygen Version: 1.5.6 Sat Oct 18 11:32:19 2008 |