vmm_hw_rtl.sv

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// 
// -------------------------------------------------------------
//    Copyright 2004-2008 Synopsys, Inc.
//    All Rights Reserved Worldwide
// 
//    Licensed under the Apache License, Version 2.0 (the
//    "License"); you may not use this file except in
//    compliance with the License.  You may obtain a copy of
//    the License at
// 
//        http://www.apache.org/licenses/LICENSE-2.0
// 
//    Unless required by applicable law or agreed to in
//    writing, software distributed under the License is
//    distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//    CONDITIONS OF ANY KIND, either express or implied.  See
//    the License for the specific language governing
//    permissions and limitations under the License.
// -------------------------------------------------------------
// 


`ifdef VMM_HW_RTL__SV
`else
`define VMM_HW_RTL__SV


//
// Select the target architecture
//
`undef VMM_HW_ARCH

`ifdef VMM_HW_ARCH_SCEMI
   // Throw a syntax error if more than one architecture was selected
   `ifdef VMM_HW_ARCH
      `VMM_HW_More_than_one_HW_platform_architecture_selected
   `endif
   `define VMM_HW_ARCH
   `define VMM_HW_RTL_USE_MODULE
`endif


`ifdef VMM_HW_ARCH_NULL
   // Throw a syntax error if more than one architecture was selected
   `ifdef VMM_HW_ARCH
      `VMM_HW_More_than_one_HW_platform_architecture_selected
   `endif
   `include "vmm.sv"
   `define VMM_HW_ARCH
   `undef VMM_HW_RTL_USE_MODULE
`endif


// Throw a syntax error if no architecture was selected
`ifdef VMM_HW_ARCH
`else
   `VMM_HW_No_HW_platform_architecture_selected
`endif


// If for simulation, always use an interface
`ifdef VMM_HW_SYNTHESIS_ON
`else
   `undef VMM_HW_RTL_USE_MODULE
`endif


// Include the DUT if mapping to hardware platform (ie. synthesis)
// or using the NULL architecture
`ifdef VMM_HW_SYNTHESIS_ON
   `define VMM_HW_INCL_DUT
`endif
`ifdef VMM_HW_ARCH_NULL
   `define VMM_HW_INCL_DUT
`endif


`ifdef VMM_HW_RTL_USE_MODULE
   `define VMM_HW_RTL_COMPONENT_START module
   `define VMM_HW_RTL_COMPONENT_END   endmodule
`else
   `define VMM_HW_RTL_COMPONENT_START interface
   `define VMM_HW_RTL_COMPONENT_END   endinterface
`endif

//
//------------------------------------------------------------------
//


`VMM_HW_RTL_COMPONENT_START vmm_hw_in_if(rx_rdy, tx_rdy, msg, uclk, urst);

   parameter width = 1;

   input              rx_rdy;
   output             tx_rdy;
   output [width-1:0] msg;
   input              uclk;
   input              urst;

`ifdef VMM_HW_SYNTHESIS_ON
`else
   integer size = width;
   string  path  = $psprintf("%m");
   reg [1024*8-1:0] ovpath = $psprintf("%m"); // For OV
`endif

`ifdef VMM_HW_ARCH_NULL
   // synthesis translate_off
   vmm_log log = new("vmm_hw_in_if", $psprintf("%m"));
   bit in_use = 0;

   reg             tx_rdy;
   reg [width-1:0] msg;

   clocking ck @(posedge uclk);
      input rx_rdy;
   endclocking

   // synthesis translate_on
`endif

`ifdef VMM_HW_SYNTHESIS_ON

   `ifdef VMM_HW_ARCH_SCEMI
      SceMiMessageInPort #(width) scemi(rx_rdy, tx_rdy, msg);
   `endif

`endif

`VMM_HW_RTL_COMPONENT_END



//
//------------------------------------------------------------------
//  
`VMM_HW_RTL_COMPONENT_START vmm_hw_out_if(tx_rdy, rx_rdy, msg, uclk, urst);
   parameter width = 1;
   parameter pri = 10;

   input               tx_rdy;
   output              rx_rdy;
   input  [width-1:0]  msg;
   input               uclk;
   input               urst;


`ifdef VMM_HW_SYNTHESIS_ON
`else
   integer size = width;
   string  path  = $psprintf("%m");
`endif

`ifdef VMM_HW_ARCH_NULL
   // synthesis translate_off
   vmm_log log = new("vmm_hw_out_if", $psprintf("%m"));
   bit in_use = 0;

   reg             rx_rdy;

   clocking ck @(posedge uclk);
      input tx_rdy;
      input msg;
   endclocking

   // synthesis translate_on
`endif


`ifdef VMM_HW_SYNTHESIS_ON

   `ifdef VMM_HW_ARCH_SCEMI
      SceMiMessageOutPort #(width, pri) scemi(tx_rdy, rx_rdy, msg);
   `endif

`endif

`VMM_HW_RTL_COMPONENT_END



//
//------------------------------------------------------------------
//  
`VMM_HW_RTL_COMPONENT_START vmm_hw_clock_control(uclk, urst,
                                                 rdy_for_cclk, cclk_en,
                                                 rdy_for_cclk_neg, cclk_neg_en);
   parameter clock_num = 1;

   output uclk;
   output urst;
   input  rdy_for_cclk;
   output cclk_en;
   input  rdy_for_cclk_neg;
   output cclk_neg_en;

`ifdef VMM_HW_ARCH_NULL
   // synthesis translate_off
   // Make sure uclk and cclk are delta-cycle aligned
   reg uclk, urst;
   always @(vmm_hw.uclk) uclk <= vmm_hw.uclk;
   always @(vmm_hw.urst) urst <= vmm_hw.urst;
   // synthesis translate_on

   reg cclk_en;
   reg cclk_neg_en;
   string path = $psprintf("%M");

   initial
   begin
      repeat (2) @ (posedge uclk);
      if (cclk_en === 1'bx || cclk_neg_en === 1'bx) begin
         $write("ERROR: clock controller %m is not associated with a clock source\n");
         $finish();
      end
   end
`endif

`ifdef VMM_HW_SYNTHESIS_ON
   `ifdef VMM_HW_ARCH_SCEMI
      SceMiClockControl #(clock_num) scemi(uclk, urst,
                                           rdy_for_cclk, cclk_en,
                                           rdy_for_cclk_neg, cclk_neg_en);
   `endif

`endif

`VMM_HW_RTL_COMPONENT_END



//
//------------------------------------------------------------------
//  
`ifdef VMM_HW_ARCH_NULL
module vmm_hw();

reg uclk;
reg urst;
reg crst;
time stamp;

int reset_cycles = 8;

initial
begin
   stamp    = 0;
   uclk     = 0;

   forever begin
      #1 uclk = 1;
      stamp = stamp + 1;
      #1 uclk = 0;
   end
end

initial
begin
   urst = 1;
   crst = 0;
   repeat (5) @ (posedge uclk);
   crst <= 1'b1;
   repeat (5) @ (posedge uclk);
   urst <= 0;
   repeat (reset_cycles * 2) @ (posedge uclk);
   crst <= 1'b0;
end

initial
begin
end

endmodule
`endif


//
//------------------------------------------------------------------
//  
`VMM_HW_RTL_COMPONENT_START vmm_hw_clock(cclk, crst, crstn);
   parameter clock_num         = 1;

   parameter ratio_numerator   = 1;
   parameter ratio_denominator = 1;
   parameter duty_hi           = 0;
   parameter duty_lo           = 100;
   parameter phase             = 0;
   parameter reset_cycles      = 8;

   output cclk;
   output crst, crstn;


`ifdef VMM_HW_ARCH_NULL
   assign crst  = vmm_hw.crst;
   assign crstn = ~vmm_hw.crst;

   int no_pos = 0; // For SV
   int no_neg = 0; // For SV
   wor no_posw;   // For Openvera
   wor no_negw;   // For Openvera

   bit ck_en;
   bit ckn_en;

   reg cclk = 0;

   // Controlled clocks must run while ccrst is asserted
   assign ck_en  = (vmm_hw.urst === 1'b0) && (cclk == 1'b0) &&
                   ((no_pos == 0 && no_posw === 1'bz) || crst);
   assign ckn_en = (vmm_hw.urst === 1'b0) && (cclk == 1'b1) &&
                   ((no_neg == 0 && no_negw === 1'bz) || crst);

   initial
   begin
      if (vmm_hw.reset_cycles < reset_cycles) begin
         vmm_hw.reset_cycles = reset_cycles;
      end

      if (ratio_numerator != ratio_denominator) begin
         $write("WARNING: Unsupported ratio for clock source %M: %0d/%0d (must be 1/1)\n",
                ratio_numerator, ratio_denominator);
      end
      if (duty_hi != 0 && duty_lo != 0) begin
         $write("WARNING: Unsupported duty cycle for clock source %M: %0d/%0d (must be 0/x or x/0)\n",
                duty_hi, duty_lo);
      end
      if (phase != 0) begin
         $write("WARNING: Unsupported phase for clock source %M: %0d (must be 0)\n",
                phase);
      end
   end

   always @ (posedge vmm_hw.uclk)
   begin
      if (vmm_hw.urst) cclk <= 1'b0;
      else begin
         if (ck_en)  cclk <= 1'b1;
         if (ckn_en) cclk <= 1'b0;
      end
   end

   string controller[$];
   logic rdy_pos[$];
   logic rdy_neg[$];

   function void why();
      if (controller.size() == 0) begin
         $write("Clock source %M does not have any associated controllers\n");
         return;
      end
      $write("State of controllers associated with %M:\n");
      $write("  Pos Neg :: Instance\n");
      foreach(controller[i]) begin
         $write("   %b   %b :: %s\n", rdy_pos[i], rdy_neg[i], controller[i]);
      end
   endfunction: why

`endif


`ifdef VMM_HW_SYNTHESIS_ON

   `ifdef VMM_HW_ARCH_SCEMI
      SceMiClockPort #(clock_num,
                       ratio_numerator, ratio_denominator,
                       duty_hi, duty_lo, phase, reset_cycles) scemi(cclk, crst);
   `endif

`endif

`VMM_HW_RTL_COMPONENT_END

`endif // VMM_HW_RTL__SV