mem_walk.sv

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00001 // 
00002 // -------------------------------------------------------------
00003 //    Copyright 2004-2008 Synopsys, Inc.
00004 //    All Rights Reserved Worldwide
00005 // 
00006 //    Licensed under the Apache License, Version 2.0 (the
00007 //    "License"); you may not use this file except in
00008 //    compliance with the License.  You may obtain a copy of
00009 //    the License at
00010 // 
00011 //        http://www.apache.org/licenses/LICENSE-2.0
00012 // 
00013 //    Unless required by applicable law or agreed to in
00014 //    writing, software distributed under the License is
00015 //    distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
00016 //    CONDITIONS OF ANY KIND, either express or implied.  See
00017 //    the License for the specific language governing
00018 //    permissions and limitations under the License.
00019 // -------------------------------------------------------------
00020 // 
00021 
00022 
00023 `include "ral_env.svh"
00024 
00025 `ifndef RAL_TB_ENV
00026 `define RAL_TB_ENV tb_env
00027 `endif
00028 
00029 
00030 program mem_walk;
00031 
00032 vmm_log log = new("Mem Walk", "Test");
00033 `RAL_TB_ENV env = new;
00034 
00035 initial
00036 begin
00037    vmm_ral_block_or_sys ral_model;
00038    vmm_ral_mem mems[];
00039 
00040    ral_model = env.ral.get_model();
00041    if (ral_model == null) begin
00042       `vmm_fatal(log, "No RAL abstraction model was specified");
00043    end
00044 
00045    env.reset_dut();
00046    ral_model.reset();
00047 
00048    // Walk over all RW memories
00049    ral_model.get_memories(mems);
00050    foreach (mems[i]) begin
00051       vmm_ral::access_e mode;
00052       string domains[];
00053       int n_bits;
00054 
00055       n_bits = mems[i].get_n_bits();
00056 
00057       // Memories may be accessible from multiple physical interfaces (domains)
00058       mems[i].get_domains(domains);
00059 
00060       // Walk the memory via each domain
00061       foreach (domains[j]) begin
00062          vmm_rw::status_e status;
00063          bit [`VMM_RAL_DATA_WIDTH-1:0] val, exp, v;
00064    
00065          // Only deal with RW memories
00066          if (mems[i].get_access(domains[j]) != vmm_ral::RW) continue;
00067 
00068          `vmm_note(log, $psprintf("Walking memory %s in domain \"%s\"...",
00069                                   mems[i].get_fullname(), domains[j]));
00070 
00071          // The walking process is, for address k:
00072          // - Write ~k
00073          // - Read k-1 and expect ~(k-1) if k > 0
00074          // - Write k-1 at k-1
00075          // - Read k and expect ~k if k == last address
00076          for (int k = 0; k < mems[i].get_size(); k++) begin
00077             mems[i].write(status, k, ~k, vmm_ral::BFM, domains[j]);
00078             if (status != vmm_rw::IS_OK) begin
00079                `vmm_error(log, $psprintf("Status was %s when writing \"%s[%0d]\" through domain \"%s\".",
00080                                          status.name(), mems[i].get_fullname(), k, domains[j]));
00081             end
00082 
00083             if (k > 0) begin
00084                mems[i].read(status, k-1, val, vmm_ral::BFM, domains[j]);
00085                if (status != vmm_rw::IS_OK) begin
00086                   `vmm_error(log, $psprintf("Status was %s when reading \"%s[%0d]\" through domain \"%s\".",
00087                                             status.name(), mems[i].get_fullname(), k, domains[j]));
00088                end
00089                else begin
00090                   exp = ~(k-1) & ((1'b1<<n_bits)-1);
00091                   if (val !== exp) begin
00092                      `vmm_error(log, $psprintf("\"%s[%0d-1]\" read back as 'h%h instead of 'h%h.",
00093                                                mems[i].get_fullname(), k, val, exp));
00094 
00095                   end
00096                end
00097 
00098                mems[i].write(status, k-1, k-1, vmm_ral::BFM, domains[j]);
00099                if (status != vmm_rw::IS_OK) begin
00100                   `vmm_error(log, $psprintf("Status was %s when writing \"%s[%0d-1]\" through domain \"%s\".",
00101                                             status.name(), mems[i].get_fullname(), k, domains[j]));
00102                end
00103             end
00104 
00105             if (k == mems[i].get_size() - 1) begin
00106                mems[i].read(status, k, val, vmm_ral::BFM, domains[j]);
00107                if (status != vmm_rw::IS_OK) begin
00108                   `vmm_error(log, $psprintf("Status was %s when reading \"%s[%0d]\" through domain \"%s\".",
00109                                             status.name(), mems[i].get_fullname(), k, domains[j]));
00110                end
00111                else begin
00112                   exp = ~(k) & ((1'b1<<n_bits)-1);
00113                   if (val !== exp) begin
00114                      `vmm_error(log, $psprintf("\"%s[%0d]\" read back as 'h%h instead of 'h%h.",
00115                                                mems[i].get_fullname(), k, val, exp));
00116 
00117                   end
00118                end
00119             end
00120          end
00121       end
00122    end
00123    
00124    env.log.report();
00125 end
00126 endprogram: mem_walk

Intelligent Design Verification
Intelligent Design Verification
Project: VMM, Revision: 1.0.0
Copyright (c) 2008 Intelligent Design Verification.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts.
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http://www.intelligentdv.com/licenses/fdl.txt
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