mem_access.sv

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00001 // 
00002 // -------------------------------------------------------------
00003 //    Copyright 2004-2008 Synopsys, Inc.
00004 //    All Rights Reserved Worldwide
00005 // 
00006 //    Licensed under the Apache License, Version 2.0 (the
00007 //    "License"); you may not use this file except in
00008 //    compliance with the License.  You may obtain a copy of
00009 //    the License at
00010 // 
00011 //        http://www.apache.org/licenses/LICENSE-2.0
00012 // 
00013 //    Unless required by applicable law or agreed to in
00014 //    writing, software distributed under the License is
00015 //    distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
00016 //    CONDITIONS OF ANY KIND, either express or implied.  See
00017 //    the License for the specific language governing
00018 //    permissions and limitations under the License.
00019 // -------------------------------------------------------------
00020 // 
00021 
00022 
00023 `include "ral_env.svh"
00024 
00025 `ifndef RAL_TB_ENV
00026 `define RAL_TB_ENV tb_env
00027 `endif
00028 
00029 
00030 program mem_access;
00031 
00032 vmm_log log = new("Mem Access", "Test");
00033 `RAL_TB_ENV env = new;
00034 
00035 initial
00036 begin
00037    vmm_ral_block_or_sys ral_model;
00038    vmm_ral_mem mems[];
00039 
00040    ral_model = env.ral.get_model();
00041    if (ral_model == null) begin
00042       `vmm_fatal(log, "No RAL abstraction model was specified");
00043    end
00044 
00045    env.reset_dut();
00046    ral_model.reset();
00047 
00048    // Access each location in all memories
00049    ral_model.get_memories(mems);
00050    foreach (mems[i]) begin
00051       vmm_ral::access_e mode;
00052       string domains[];
00053       int n_bits;
00054 
00055       // Can only deal with memories with backdoor access
00056       if (mems[i].get_backdoor() == null) begin
00057          `vmm_warning(log, $psprintf("Memory \"%s\" does not have a backdoor mechanism available",
00058                                      mems[i].get_fullname()));
00059          continue;
00060       end
00061 
00062       n_bits = mems[i].get_n_bits();
00063 
00064       // Memories may be accessible from multiple physical interfaces (domains)
00065       mems[i].get_domains(domains);
00066 
00067       // Walk the memory via each domain
00068       foreach (domains[j]) begin
00069          vmm_rw::status_e status;
00070          bit [`VMM_RAL_DATA_WIDTH-1:0] val, exp, v;
00071       
00072          `vmm_note(log, $psprintf("Accessing memory %s in domain \"%s\"...\n",
00073                                   mems[i].get_fullname(), domains[j]));
00074 
00075          mode = mems[i].get_access(domains[j]);
00076 
00077          // The access process is, for address k:
00078          // - Write random value via front door
00079          // - Read via backdoor and expect same random value if RW
00080          // - Write complement of random value via back door
00081          // - Read via front door and expect inverted random value
00082          for (int k = 0; k < mems[i].get_size(); k++) begin
00083             val = $random & ((1'b1<<n_bits)-1);
00084             if (mode == vmm_ral::RO) begin
00085                mems[i].peek(status, k, exp);
00086                if (status != vmm_rw::IS_OK) begin
00087                   `vmm_error(log, $psprintf("Status was %s when reading \"%s[%0d]\" through backdoor.",
00088                                             status.name(), mems[i].get_fullname(), k));
00089                end
00090             end
00091             else exp = val;
00092 
00093             mems[i].write(status, k, val, vmm_ral::BFM, domains[j]);
00094             if (status != vmm_rw::IS_OK) begin
00095                `vmm_error(log, $psprintf("Status was %s when writing \"%s[%0d]\" through domain \"%s\".",
00096                                          status.name(), mems[i].get_fullname(), k, domains[j]));
00097             end
00098 
00099             val = 'x;
00100             mems[i].peek(status, k, val);
00101             if (status != vmm_rw::IS_OK) begin
00102                `vmm_error(log, $psprintf("Status was %s when reading \"%s[%0d]\" through backdoor.",
00103                                          status.name(), mems[i].get_fullname(), k));
00104             end
00105             else begin
00106                if (val !== exp) begin
00107                   `vmm_error(log, $psprintf("Backdoor \"%s[%0d]\" read back as 'h%h instead of 'h%h.",
00108                                             mems[i].get_fullname(), k, val, exp));
00109                end
00110             end
00111 
00112             exp = ~exp & ((1'b1<<n_bits)-1);
00113             mems[i].poke(status, k, exp);
00114             if (status != vmm_rw::IS_OK) begin
00115                `vmm_error(log, $psprintf("Status was %s when writing \"%s[%0d-1]\" through backdoor.",
00116                                          status.name(), mems[i].get_fullname(), k));
00117             end
00118 
00119             mems[i].read(status, k, val, vmm_ral::BFM, domains[j]);
00120             if (status != vmm_rw::IS_OK) begin
00121                `vmm_error(log, $psprintf("Status was %s when reading \"%s[%0d]\" through domain \"%s\".",
00122                                          status.name(), mems[i].get_fullname(), k, domains[j]));
00123             end
00124             else begin
00125                if (mode == vmm_ral::WO) begin
00126                   if (val !== '0) begin
00127                      `vmm_error(log, $psprintf("Front door \"%s[%0d]\" read back as 'h%h instead of 'h%h.",
00128                                                mems[i].get_fullname(), k, val, 0));
00129                   end
00130                end
00131                else begin
00132                   if (val !== exp) begin
00133                      `vmm_error(log, $psprintf("Front door \"%s[%0d]\" read back as 'h%h instead of 'h%h.",
00134                                                mems[i].get_fullname(), k, val, exp));
00135                   end
00136                end
00137             end
00138          end
00139       end
00140    end
00141    
00142    env.log.report();
00143 end
00144 endprogram: mem_access

Intelligent Design Verification
Intelligent Design Verification
Project: VMM, Revision: 1.0.0
Copyright (c) 2008 Intelligent Design Verification.
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