Modules

Functions
module	dut (input clk, input rst, input rsttst)
	VMM Test: Device Under Test.
module	tb_top ()
	VMM Test: Testbench Top.

---

Function Documentation

module dut	(	input	clk,
		input	rst,
		input	rsttst
	)

VMM Test: Device Under Test.

A simple dut - has a clock and reset. Has a reset test (rsttst) port for testing the reset transactor / monitor.

Parameters:

	clk	input - dut clock
	rst	input - dut reset
	rsttst	input - reset test port

Definition at line 63 of file dut.sv.

module tb_top

(

)

VMM Test: Testbench Top.

The signal layer top file - "Testbench Top."
This module instantiates all of the signal layer components including the DUT, interfaces, and clock generator.

Definition at line 62 of file tb_top.sv.