SystemVerilog Reset Transaction / Transactor Library Released
Wednesday, August 19th, 2009I’ve created and released a randomizable SystemVerilog reset transaction / transactor library. Not only is this library useful for those simply looking for a randomized mechanism for sending reset(s) to a device under test (DUT), it is also useful for those of you looking to see how to build a transaction based bus functional model / monitor in both a generic and VMM 1.1 style. The generic models are wrapped with their VMM counterparts and are tested using a VMM environment and signal layer.
Shows how to:
- build a modern randomized SystemVerilog verification component / transaction in a generic fashion
- integrate a generic transaction / component into the VMM
- write a VMM transaction / transactor driver / transactor monitor
- build a VMM environment and signal layer
- connect a DUT to a class based testbench using interfaces with modport, clocking blocks and virtual interfaces
- use SystemVerilog constraints to get a desired result
- implement functional coverage
- use VMM callbacks to collect functional coverage
- create (and run) tests in the VMM style (vmm_test) – by instantiating and constraining the environment
Can be used to:
- drive one (or more) active high or low reset(s)
- drive a sync/async assert/deassert reset
- drive reset for a specific or random range duration
- assert / deassert asynchronously randomly within the clock period
- monitor existing reset(s) for coverage
- can be driven with transactions or with direct method calls of the bfm methods
All of the SystemVerilog library source code including the code required to document and run the environment are available to download here:
http://www.intelligentdv.com/downloads/index.html#svreset
The library is fully documented with doxygen and that documentation is available here:
http://www.intelligentdv.com/documents/index.html#resetdox
The complete details of what the library includes are after the break.