Finally! A Doxygen filter for SystemVerilog available for free as GPL open source. (And I do mean finally!)
Are you still using MS Word to document your verification environment? Is your documentation out of date as soon as you send your final draft to the printer? Is your boss constantly hounding you about documenting your verification environment? Are you still trying to figure out how to leverage SciTE to generate pretty documentation? Are your coworkers struggling to extend your simple base class?
Well no more! Grab this filter along with my other doxygen tools, do a little light reading (and optionally a little more reading), edit a simple makefile and then â€“ bam â€“ peruse your code in doxygen documentation glory.