IDV has just acquired a license for the Synopsys VCSi simulator!

The simulator is easy to use – and has a simple cli interface and a powerful GUI.  I’ve been using this simulator with great success at my day job for years.

Now that I have a simulator I’ve started developing source to share with the community, starting with a collection of SystemVerilog examples.

I learned SV by coding little snippets when I wanted to understand a concept; and now you can too!

The first example is a simple ‘Hello World’ program.  Really the first program is just a template for any other example.  It includes a pretty clean makefile (for VCS) and an empty canvas program block.

Usage:

If you use VCS at your work then you can use the makefile. You will likely have to assign the VCS variable to vcs (it is currently assigned to vcsi – the version of vcs that I am using here.)

I’d love to add Mentor’s Questa support to the makefile.  If you use Questa then please take a look and let me know what additions / changes would be required to run Questa in a batch mode. And – if you happen to work for mentor, and can get me a Questa license, then please drop me a line!

Runtime usage – the makefile has the following targets:

• make           — compile and run the example
• make run       — compile and run the example
• make gui       — compile and run the example using DVE
• make covreport — generate and view coverage report
• make cov       — generate coverage report
• make simv      — compile the example
• make tar       — create bz2 compressed tarball of this example (including log and dump)
• make clean     — delete all generated files (excluding log and dump)
• make cleanall  — delete all generated files (including log and dump)

The tar target is handy when you find a simulator issue that you need to share with your simulator vendor.

If you are writing an example that doesn’t include DPI-C code or RTL then no edits of the makefile should be required.

To make your own example:

• Edit the main.sv file to create your example code – and then just type make.
• Including additional testbench SV files:
  • just use the `include “yourfile.sv” in main.sv.
  • if the included files are in sub-dirs then edit the Makefile variable “INCDIR” to include your sub-dirs
  • if you include correctly the TBFILES should not have anything other than main.sv
• Including DPI-C C files:
  • set the CPPFILES variable with a space delimited list of the files
• Including RTL Verilog files:
• set the RTLFILES variable with a space delimited list of the files

You can download the examples as a tarball here:

http://intelligentdv.com/downloads/index.html#svexamples

If you have any issues please file a bug to the SVexamples project here:

http://bugs.intelligentdv.com

If you have any requests for examples you can file them there as well.

AND – if you have some examples that you’d like to share you can upload them through the bugtracker too!

-Hello, World

This entry was posted on Monday, March 9th, 2009 at 12:00 am and is filed under SystemVerilog. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.