A new release to the SV simulation timers is now available!

This release includes

• fix for potential race condition on restart [#37]
• fix for issue with timescale in the tests [#36]
• proper use of ID for OVM console log reporting

You can see the doxygen documentation for this release here:

http://intelligentdv.com/documents/index.html#timersdox

Note that the doxygen documentation for the SV Timers includes comments on how to use the timers in base, OVM, and VMM forms.

And you can download the release here:

http://intelligentdv.com/downloads/index.html#svtimers

If you find any bugs please file them to the bug tracker here:

http://intelligentdv.com/bugs/

-DinDinDing!

This entry was posted on Thursday, June 25th, 2009 at 10:00 pm and is filed under SystemVerilog. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.